A semiconductor device in which an electrically-rewritable nonvolatile memory and a microcomputer are mix mounted on a single silicon substrate is widely used in industrial machines, home electronics, vehicle-installed devices, and the like as an embedded microcomputer.
The nonvolatile memory of the above-described semiconductor device stores programs required by the microcomputer, and the programs are read to use as needed. As cell structures of the nonvolatile memory suitable for such a mix mounting, there is a split gate memory cell in which a select MOS (metal oxide semiconductor) transistor and a memory MOS transistor are connected in series.
Among split gate memory cells, more particularly, in a memory cell structure in which a gate electrode of the memory MOS transistor (hereinafter, referred to as a memory gate) is disposed on a sidewall of a gate electrode of the select MOS transistor (hereinafter, referred to as a select gate) by utilizing a self-alignment technique, a gate length of the memory gate can be shorten to a minimum resolution size of lithography or less, and therefore, it is known to achieve a finer memory cell compared with a memory cell structure in which a select gate and a memory gate are individually formed by etching with using a photoresist film as a mask (for example, Japanese Patent Application Laid-Open Publication No. 2003-046002 (Patent Document 1)).
The memory MOS transistor among the two types of MOS transistors constituting the split gate memory cell stores information by retaining charges in a gate insulating film, and there are mainly two types for this charge retention. One of them is a floating-gate type (for example, Japanese Patent Application Laid-Open Publication No. 2004-363122 (Patent Document 2)) using an electrically-isolated conductive polycrystalline silicon film for a part of the gate insulating film, and the other is a MONOS (Metal Oxide Nitride Oxide Semiconductor) type (for example, Patent Document 1) storing charges in an insulating film such as a silicon nitride film having a property of storing charges.
In both of the above-described two charge-retaining types, a silicon dioxide film having an excellent insulating property is inserted between a charge-storing region and a silicon substrate. However, in the floating-gate type, if a local leakage path occurs in the silicon dioxide film, there is a problem that the charges cannot be retained since the retained charges are leaked to the substrate side through the leakage path. On the other hand, in the MONOS type, there is an advantage that merely the retained charges around the leakage path are leaked since the retained charges are spatially dispersed in the insulating film which is the charge-trapping film, so that extreme reduction in charge retention life does not occur.
FIG. 41 illustrates a cross-sectional structure of a memory cell employing the MONOS type as the charge-retaining method among the split gate memory cells utilizing a self-alignment technique. The memory cell is composed of a select MOS transistor and a memory MOS transistor. After a select gate 8 is formed, a memory gate 15 is formed on a sidewall of the select gate 8 via a gate insulating film 52 in a self-aligning manner. A gate insulating film 54 in the select MOS transistor is composed of a silicon dioxide film, and the gate insulating film 52 in the memory MOS transistor is composed of a triple-layer film in which a bottom oxide film 52a of a first potential barrier film, a silicon nitride film 52b of a charge-trapping film, and a top oxide film 52c of a second potential barrier film are stacked in this order. Although not illustrated, the select gate 8 is connected to a select gate line, and the memory gate 15 is connected to a word line, respectively. Also, a source region 55 in the select MOS transistor is connected to a common source line, and a drain region 56 in the memory MOS transistor is connected to a data line, respectively.
Writing to the memory cell is carried out by turning the select MOS transistor to be on-state and applying a predetermined voltage to the drain region 56 and the memory gate 15 in the memory MOS transistor at the same time. At this time, when setting a condition which generates a high electric field at a boundary region between the select MOS transistor and the memory MOS transistor, hot electrons are generated on a surface of a p-type well 3 in this region, and a part of the hot electrons is injected to the memory gate 15 side (SSI: Source Side Injection). The injected hot electrons are trapped by the silicon nitride film 52b which is a part of the gate insulating film 52 in the memory MOS transistor to write information. On the other hand, erasing of the information is carried out by applying a negative bias and a positive bias to the memory gate 15 and the drain region 56, respectively to generate hot holes by using band-to-band tunneling, and neutralizing the electrons by injecting the hot holes into the silicon nitride film 52b (hot-hole erase).